Charge trap semiconductors have become commercially viable for use in flash memory devices. In recent years, three-dimensional charge-trap semiconductor devices have been developed, which allow for memory cells to be constructed in both a horizontal and vertical matrix, thereby increasing memory capacity.
FIG. 1 illustrates one embodiment of three-dimensional charge-trap semiconductor device 100. The semiconductor device 100 includes a plurality of channel devices 140 vertically supported by a substrate 110. A cross-sectioned channel device 140A is illustrated in the foreground of FIG. 1 for ease of understanding, and is representative of each of the other channel devices 140. As can be seen from the channel device 140A, the channel devices 140 each pass through a corresponding select gate 170 and a plurality of control gates 160. Shortly before reaching the control gates 160, the channel device 140A becomes surrounded by a charge trap layer 150A (e.g., an ONO layer). Similar charge trap layers 150 are disposed on the other channel devices 140 at or near the control gates 160.
A memory cell is represented by each overlapping combination of a control gate 160 with a channel device 140 and ONO layer 150. The channel devices 140 are connected between corresponding bit lines 120 and source lines 130 used for addressing the various memory cells.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical or similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.